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W631GG6KB
8. FUNCTIONAL DESCRIPTION
8.1
Basic Functionality
The DDR3 SDRAM is a high-speed dynamic random-access memory internally configured as an
eight-bank DRAM. The DDR3 SDRAM uses an 8n prefetch architecture to achieve high-speed
operation. The 8n prefetch architecture is combined with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM consists
of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-
bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3 SDRAM are burst oriented, start at a selected location, and
continue for a burst length of eight or a ?chopped‘ burst of four in a programmed sequence. Operation
begins with the registration of an Active command, which is then followed by a Read or Write
command. The address bits registered coincident with the Active command are used to select the
bank and row to be activated (BA0-BA2 select the bank; A0-A12 select the row). The address bits
registered coincident with the Read or Write command are used to select the starting column location
for the burst operation, determine if the auto precharge command is to be issued (via A10), and select
BC4 or BL8 mode ?on the fly‘ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3 SDRAM must be powered up and initialized in a predefined
manner. The following sections provide detailed information covering device reset and initialization,
register definition, command descriptions, and device operation.
8.2
8.2.1
RESET and Initialization Procedure
Power-up Initialization Sequence
The following sequence is required for POWER UP and Initialization.
1. Apply power (RESET# is recommended to be maintained below 0.2 * V DD ; all other inputs may be
undefined). RESET# needs to be maintained for minimum 200 μS with stable power. CKE is pulled
―Low‖ anytime before RESET# being de -asserted (min. time 10 nS). The power voltage ramp time
between 300 mV to V DD min. must be no greater than 200 mS; and during the ramp, V DD ≥ V DDQ
and (V DD - V DDQ ) < 0.3 Volts.
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V DD and V DDQ are driven from a single power converter output, AND
The voltage levels on all pins other than V DD , V DDQ , V SS , V SSQ must be less than or equal to
V DDQ and V DD on one side and must be larger than or equal to V SSQ and V SS on the other side.
In addition, V TT is limited to 0.95 V max once power ramp is finished, AND
V REF tracks V DDQ /2.
Apply V DD without any slope reversal before or at the same time as V DDQ .
Apply V DDQ without any slope reversal before or at the same time as V TT & V REF .
The voltage levels on all pins other than V DD , V DDQ , V SS , V SSQ must be less than or equal to
V DDQ and V DD on one side and must be larger than or equal to V SSQ and V SS on the other side.
2. After RESET# is de-asserted, wait for another 500 μS until CKE becomes active. During this time,
the DRAM will start internal state initialization; this will be done independently of external clocks.
3. Clocks (CK, CK#) need to be started and stabilized for at least 10 nS or 5 t CK (which is larger)
before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to
clock (t IS ) must be met. Also, a NOP or Deselect command must be registered (with t IS set up time
to clock) before CKE goes active. Once the CKE is registered ―High‖ after Reset, CKE need s to be
continuously registered ―High‖ until the initialization sequence is finished, including expiration of
t DLLK and t ZQ init.
Publication Release Date: Dec. 09, 2013
Revision A05
- 12 -
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